The present invention relates to a semiconductor device and a capacitance regulation circuit, and more particularly, to a insulated gate semiconductor device such as MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), insulated gate bipolar transistor (IGBT), and injection enhanced gate transistor (IEGT), and to a capacitance regulation circuit which adjusts the capacitance of these semiconductor devices dynamically.
In order to use electric energy effectively, power converters, such as an inverter, are used widely. And as a semiconductor device for electric power control used for these power converters, the insulated gate semiconductor devices which have an excellent controllability are being used mainly. In particular, the loss of the IGBTs has become lower and the blocking voltage thereof has become higher, and their application field has spread even into the fields of higher blocking voltage and the larger current, for which the GTO thyristors were used conventionally.
Since the insulated gate semiconductor devices such as IGBT etc. have a wide safe operating area, they do not need protection circuits, such as a snubber circuit used with the GTO (Gate Turn Off) thyristors conventionally. Moreover, in recent years, further reduction of switching loss has been achieved by reducing the impedance (gate resistance) of a gate drive circuit, and by switching at higher speed.
However, these measures produce a high rate of voltage change (dV/dt) and a high rate of current change (dI/dt). Furthermore, high dI/dt produces a surge voltage and a even higher dV/dt by synergy with the parasitic inductance of a circuit.
As a result, the insulated gate semiconductor device may have a bad influence on peripheral equipment by emitting a noise out of the device, or malfunction may arise because device's own gate voltage is changed. Furthermore, an excessive surge voltage may also cause the destruction of insulated gate semiconductor chip and/or a free wheeling diode (FWD) chip connected in parallel to the insulated gate semiconductor chip.
Particularly, although when the insulated gate semiconductor chip is turned on the FWD which is connected to the turned on chip in series and forms the arm of a bridge circuit will carry out reverse recovery operation, when dV/dt of FWD becomes high there becomes a danger that the gate of the IGBT which is connected in parallel to the FWD and should be in the OFF state may be charged and malfunction (turning into ON state) may occur.
Hereafter, this malfunction will be explained accompanying IGBT as a example, referring to FIG. 29.
That is, the circuit shown in this figure has the arm which consists of a first switching device in which IGBT1 and FWD1 are connected in parallel in opposite directions, and a second switching device in which IGBT2 and FWD2 are connected in parallel in opposite directions. A load is connected to the node of connection of the first switching device and the second switching device. In addition, although only one arm is illustrated in FIG. 29, the bridge circuit including another arm which is not illustrated is formed in an actual circuit.
Now, if turn-on of IGBT2 is carried out from the state where FWD1 is free wheeling the load current, FWD1 performs reverse recovery operation and the voltage Vka1 between cathode-anode of FWD1 rises at the same time IGBT2 becomes in a ON state and the voltage Vce2 between the collector and the emitter of IGBT2 will fall. Then, although IGBT1 is in the OFF state where its gate is reverse biased, dVcg/dt which is almost equivalent to dVka1/dt is applied between the collector and the gate, and then a displacement current occurs in the parasitic capacitance Ccg between them.
This displacement current has an effect of charging the parasitic capacitance Cge between the gate and the emitter of IGBT1 in the direction corresponding to a forward bias of the voltage Vge1 between the gate and the emitter of IGBT1. And if Vge1 exceeds a threshold value Vth, IGBT1 will carry out malfunction (turn-on), and a short circuit will be formed. This malfunction tends to happen, when dVka1/dt is high, or when the Ccg/Cge ratio of IGBT is high. Meanwhile, although another parasitic capacitance also exists between the collector and the emitter of IGBT, it is not illustrated since it is unrelated to the operation mentioned above.
Although high-speed switching obtained by a reduction of gate resistance of the gate drive circuit exactly reduces the turn-on loss Eon of IGBT, since dI/dt and dV/dt become high in connection with it, it will make the reverse recovery loss Err of FWD occurred simultaneously increase. Particularly, when excessive dI/dt and dV/dt occur, a large electric power arises momentarily in FWD and the problem that FWD may breaks occurs. That is, since the problems that Err of FWD increases and that FWD breaks occurred, there was a limit in making the switching speed higher, and consequently, there was a limit in reducing the total loss of the power converter.
In order to solve these problems, as illustrated in FIG. 30, a trial to suppress the generation of a noise or change in the voltage Vge between the gate and the emitter was carried out by connecting a capacitor CGE between the gate terminal and the emitter terminal of the semiconductor device containing an insulated gate semiconductor chips (IGBT is shown in this figure as an example). However, since the switching time and Eon increase because of the capacitor CGE, techniques to make the capacitance between the gate and the emitter inside the semiconductor device small, and to connect the minimum capacitor CGE if needed at the time of operation has been taken.
However, it was difficult to stably suppress the change of Vge of the insulated gate semiconductor chip itself by such conventional techniques, because of the impedance inside the semiconductor device, the impedance up to the connection point of the capacitor CGE connected at the exterior of the semiconductor device, and the inductance of the CGE itself. Especially, in the large-sized package for the large current capacity which includes many insulated gate semiconductor chips, since the gate wiring in a package becomes long, the parasitic inductance cannot be disregarded. Therefore, gate resistances rg need to be provided in each chip in order to suppress the oscillation phenomenon due to the parasitic inductance.
As a result, it was difficult to stably suppress the changes in Vge for every chip with the conventional structure. Moreover, connecting the capacitor outside the device had the problem of not being mechanically reliable.
On the other hand, a semiconductor device to which capacitor CGE is added on the substrate on which the insulated gate semiconductor chip is mounted is disclosed in Japanese Patent Laid-Open Publication No. 2000-243905. That is, it becomes possible to suppress the change in Vge and to improve the mechanical reliability to some extent by incorporating capacitor CGE on the mounting substrate in the semiconductor device.
However, as a result of original examination by the inventors, it has become clear that there was room for the further improvement in the semiconductor device disclosed in Japanese Patent Laid-Open Publication No. 2000-243905. That is, since the generation of heat from the insulated gate semiconductor chip is relatively large, if capacitor CGE is mounted on the same mounting substrate as the insulated gate semiconductor chip, the influence of the rise of temperature cannot be disregarded.
Specifically, the maximum temperature of the substrate on which the insulated gate semiconductor chips, such as IGBT, are mounted may rise up to even about 125 degrees centigrade during operation. As a result, there is a possibility that the thermal fatigue of solder which mounts capacitor CGE may arise. Moreover, since there is “variation” in a temperature coefficient for each capacitor CGE, there is a possibility that the switching operation of two or more chips provided in the same equipment becomes less uniform.
Furthermore, if the insulated gate semiconductor chips which serve as a heat source are separated from the capacitors CGE in order to prevent these problems, it becomes necessary to enlarge the mounting substrate, and as a result, the size of the semiconductor device becomes enlarged.
As mentioned above, when gate resistance is reduced for the reduction of loss in the conventional insulated gate semiconductor device, high dI/dt, high dV/dt, and a high surge voltage may occur, IGBT/FWD may be broken, the noise may be emitted to the environment, and malfunction may be carried out by its own change of Vge.
Moreover, there was a limit in reduction of total loss including IGBT and FWD.
Furthermore, since the impedance from each chip was not able to be disregarded in a large-sized insulated gate semiconductor device by the method of connecting the external capacitor CGE to the exterior of the semiconductor device, it was difficult to stably suppress change in Vge of the semiconductor chips.
Furthermore, when the capacitors CGE are incorporated on the same mounting substrate as the insulated gate semiconductor chips, there is concern about the influence by heat.